1. Field of the Invention
The present invention relates to the field of electronic circuits providing or exploiting a logic signal.
According to a first aspect, the present invention more specifically relates to the forming of a fast logic circuit, for example implementing a non-inverting function. This type of circuit is, for example, used to adapt the level of a logic input signal and is generally designated as a buffer.
2. Discussion of the Related Art
FIG. 1 shows the conventional symbol of such a logic circuit. Circuit 1 includes two supply terminals 2, 3 respectively connected to voltages VDD and GND, the latter generally representing the ground. An input terminal 4 of circuit 1 receives a logic signal IN. Circuit 1 provides, on an output terminal 5, a signal OUT having the same state as input signal IN.
FIG. 2 shows an example of an internal structure of a non-inverting logic circuit 1 in bipolar technology. This circuit essentially includes two transistors, TP1 of PNP type and TN1 of NPN type. Transistor TP1 is the input transistor. Its base is connected to terminal 4 by an input resistor Re1. The emitter of transistor TP1 is connected, by a biasing resistor Rp1, to terminal 2 at voltage VDD. The collector of transistor TP1 is connected to the base of transistor TN1. The emitter of transistor TN1 is connected to ground terminal 3. The collector of transistor TN1 forms output 5 terminal of circuit 1 and is connected, by a resistor Rn, to terminal 2.
The static operation of circuit 1 is the following. If input signal IN is low (ground GND), transistor TP1 is on. Transistor TN1 receives a base current. It is thus also on, and output signal OUT is also low. If the input signal is high (for example, voltage VDD), transistor TP1 is off. No base current is provided to transistor TN1, which is accordingly also off. Output signal OUT then is high, a current flowing through resistor Rn.
FIGS. 3A and 3B illustrate, with timing diagrams, the dynamic operation of the circuit of FIG. 1. FIG. 3A shows an example of the course of input signal IN. FIG. 3B illustrates the corresponding course of output signal OUT.
It is assumed that initially, signal IN is low and that it switches to a high state (voltage V1) at a time t1. The level of signal IN may be different from voltage VDD provided that it is (neglecting the voltage drop in resistor Re1) greater than VDD-VbeP, where VbeP represents the base-emitter voltage of transistor TP1 (approximately 0.6 V). Signal OUT takes a certain time to reach the high level (VDD, neglecting the voltage drop in resistor Rn). The time of switching to the high state (times t1 to t2) essentially depends on the time taken by output transistor TN1 to desaturate. Indeed, when transistor TP1 turns off, charges remain accumulated in the base of transistor TN1 and a certain time is necessary to evacuate them by leakage currents.
The desaturation time of transistor TN1 also depends on:                the output impedance of circuit 1, which cannot be controlled in the forming of the logic circuit itself;        the time taken by transistor TP1 to desaturate by evacuating the charges from its collector into the base of transistor TN1; and        the base current received by transistors TN1 and TP1 upon switching to the low state. The greater these currents, the more time it takes for the transistors to desaturate.        
In FIG. 3A, it is assumed that signal IN switches low at a time t3. The circuit switching is fast in this way and signal OUT reaches the low state at a time t4 close to time t3. Generally the time of switching to the low state is negligible (shorter than 100 nanoseconds). However, the output signal rise time is relatively long, for example, on the order of one microsecond.
A conventional solution to accelerate the rise time is to decrease the base current injected into transistor TN1 upon switching to the low state. For this purpose, the gain of transistor TP1 is decreased or its biasing resistance Rp1 is increased. However, the base current of transistor TN1 must respect the condition of being sufficient to enable its saturating, failing which the switching to the low state will not occur. Further, a significant base current enables fast switching to the high state. Accordingly, a compromise providing the above switching times must most often be made.
Another solution is to provide an additional resistor between the base and the emitter of transistor TN1. However, this solution only has a limited effect since the value of this resistance must still enable saturation of transistor TN1 upon switching to the low state. Further, it causes additional power consumption.
In some applications (for example, in applications where the input terminal may remain unconnected), it is generally desired to minimize the circuit power consumption when the input is high or unconnected. In the circuit of FIG. 2, this condition is fulfilled by the fact that, in the high state, both transistors TP1 and TN1 are off, the power consumption being then limited to that of resistor Rn.